1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more specifically, it relates to a semiconductor integrated circuit device having a plurality of output buffer circuits, which can output a plurality of data in parallel with each other.
2. Description of the Background Art
Following increase of the storage capacity of a dynamic semiconductor memory device (hereinafter referred to as a DRAM) or a static semiconductor memory device (hereinafter referred to as an SRAM), bit multiplication of a data input/output structure is now under way for increasing the bit width of simultaneously inputted/outputted data. If data are inputted/outputted with a narrow bit width, the flexibility of system design is disadvantageously restricted.
When the memory capacity required by a system and the bit width of inputted/outputted data are constant, the system can be configured with a smaller number of chips as the bit width of data inputted/outputted in/from each chip increases following increase of the storage capacity of the semiconductor memory device per chip.
If a system requires a memory capacity of 4 MB, for example, 32 semiconductor chips in total are necessary for configuring the corresponding memory system with those of a 1 M.times.1 structure, while only two semiconductor chips are necessary when employing those of a 1 M.times.16 structure.
When extending a memory system having a large memory capacity per chip, on the other hand, the memory capacity of the extension unit unnecessarily increases if the bit width of inputted/outputted data remains constant.
Consider the case of extending a memory system configured by eight DRAMs of a 256 K.times.4 structure with four DRAMs of a 4 M.times.4 structure having a storage capacity of 16 times per chip with a constant bit width of inputted/outputted data. In this case, the capacity of the memory system extended with four DRAMs of the 4 M.times.4 structure is expanded from 1 MB to 16 MB at a stretch. If DRAMs having a 1 M.times.16 data input/output structure per chip, for example, can be employed, however, an extension unit for the memory system having a memory capacity of 4 MB can be formed with two chips.
In either case, therefore, the whole system can be miniaturized with a multi-bit structure following increase of the storage capacity per chip.
However, such increase of the bit width of simultaneously outputted data results in the following problem:
FIG. 1 is a schematic block diagram showing the structure of an output buffer circuit 1000 according to first prior art.
The following description is made with reference to a DRAM as a semiconductor integrated circuit device.
Referring to FIG. 1, the conventional output buffer circuit 1000 includes an output preamplifier 1 for amplifying and outputting data read from a memory cell, an output control circuit 2 for controlling the timing for outputting the data, a NAND circuit 3 receiving the output of the output preamplifier 1 and a control signal from the output control circuit 2, an invertor 10 receiving the output of the output preamplifier 1, a NAND circuit 4 receiving an output of the invertor 10 and the control signal from the output control circuit 2, and invertors 11 and 12 receiving outputs from the NAND circuits 3 and 4 respectively.
The output buffer circuit 1000 further includes an N-channel MOS transistor 5 connected between a data output terminal 7 and a power supply line 8 supplying a power supply potential Vcc with its gate potential controlled by the invertor 11, and an N-channel MOS transistor 6 connected between the data output terminal 7 and a ground line 9 supplying a ground potential GND with its gate potential controlled by the invertor 12.
Operations of the output buffer circuit 1000 are now briefly described.
FIG. 2 is a timing chart showing the potentials of the respective parts and time changes of currents during the operations of the output buffer circuit 1000.
In the following description, symbols P, Q, R and S denote output nodes of the output preamplifier, the output control circuit 2, the invertor 11 and the invertor 12 respectively. Further, symbols V.sub.P, V.sub.Q, V.sub.R and V.sub.S denote the potentials of the output nodes P, Q, R and S respectively, and symbol V.sub.OUT denotes the potential of the data output terminal 7.
Referring to FIG. 2, the output potentials V.sub.R and V.sub.S of the invertors 11 and 12 are at low levels during times t0 and t1 when the output potential V.sub.Q of the output control circuit 2 is at a low level, whether the level of the output potential V.sub.P of the preamplifier 1 is high or low. Therefore, both N-channel MOS transistors 5 and 6 are cut off, and the data output terminal 7 enters a high impedance (Hi-Z) state.
When the output potential V.sub.Q of the output control circuit 2 goes high at a time t2, the output potential V.sub.R of the invertor 11 goes high while the output potential Vs of the invertor 12 remains low in response to the output potential V.sub.P, which is at a high level.
The N-channel MOS transistor 5 responsively enters a conducting state, and the potential of the data output terminal 7 starts to rise in response to this transition. A current i1 for charging a load connected to the data output terminal 7 flows to the N-channel MOS transistor 5. In response to this, noise appears on the potential level of the power supply line 8 supplying the power supply potential Vcc.
When the output potential V.sub.Q of the output control circuit 2 goes low at a time t3, the N-channel MOS transistor 5 enters a non-conducting state again and the data output terminal 7 returns to the Hi-Z state in response thereto.
Thereafter the potential V.sub.Q goes high at a time t4, and the N-channel MOS transistor 6 in turn enters a conducting state while the potential level of the data output terminal 7 starts to drop in response to the potential V.sub.P, which is now at a low level. At this time, a current i2 for discharging the data output terminal 7 and the load connected thereto flows to the N-channel MOS transistor 6 entering the conducting state. Noise is superposed on the potential level V.sub.GND of the ground line 9 supplying the ground potential GND, due to this current i2.
When the potential V.sub.P goes high at a time t5 while the output potential V.sub.Q of the output control circuit 2 remains high, the N-channel MOS transistor 6 enters a non-conducting state and the N-channel MOS transistor 5 enters a conducting state in response thereto. The current i1 necessary for charging the data output terminal 7 and the load connected thereto from a low level to a high level flows to the N-channel MOS transistor 5. In other words, the potential of the data output terminal 7 fully swings from a low level to a high level. Therefore, the value of the current i1 is larger than that at the time t2. Thus, noise superposed on the power supply line 8 for supplying the power supply potential Vcc is at a higher level than that appearing after the time t2.
Further, the potential V.sub.P changes from the high level to a low level at a time t6 while the potential V.sub.Q remains high. At this time, the N-channel MOS transistor 5 enters a non-conducting state and the N-channel MOS transistor 6 enters a conducting state, contrarily to the states at the time t5. Thus, the potential of the data output terminal 7 fully swings from the high level to a low level. Therefore, the value of the discharge current i2 flowing through the N-channel MOS transistor 6 is larger than that at the time t4. Thus, noise superposed on the potential V.sub.GND after the time t6 is at a higher level than that superposed after the time t4.
The above description has been made on the noise superposed on the potentials Vcc and V.sub.GND of the power supply line 8 and the ground line 9 when only the output buffer circuit 1000 corresponding to the data output terminal 7 operates. However, a recent DRAM has a larger number of simultaneously operating output buffer. The power supply line 8 and the ground line 9 supply the power supply potential Vcc and the ground potential V.sub.GND to such a plurality of output buffer. When the plurality of output buffer circuits simultaneously operate, therefore, noise superposed on the power supply line 8 and the ground line 9 exerts more serious influence.
Referring to FIG. 2, dotted lines on the potentials Vcc and V.sub.GND show coupling noise caused by a capacitance present between the power supply line 8 and the ground line 9. In other words, noise superposed on the power supply line 8 causes noise not only on the potential level of the power supply line 8 but also on that of the ground line 9. This coupling noise may further unstabilize the circuit operations.
FIG. 3 is a schematic block diagram showing the structure of an output buffer circuit 1200 capable of reducing occurrence of noise, which is disclosed in Japanese Patent Laying-Open No. 1-149518 (1989).
The output buffer circuit 1200 according to second prior art is different in structure from the output buffer circuit 1000 according to the first prior art mainly in the following points:
First, the output buffer circuit 1200 includes two N-channel MOS transistors 27 and 28 as transistors for discharging a data output terminal 25 and a load connected thereto.
Second, a signal for controlling the gate potential of the N-channel MOS transistor 28 is delayed by a delay time of a delay circuit 26 as compared with that for controlling the gate potential of the N-channel MOS transistor 27.
While the output buffer circuit 1200 according to the second prior art is further different from the output buffer circuit 1000 according to the first prior art in a point that a P-channel MOS transistor 23 is employed as a transistor for charging the data output terminal 25 and the load connected thereto, this difference is not essential as described later.
In the following description, symbols P, Q and R denote nodes of gates of the P-channel MOS transistor 23, the N-channel MOS transistor 27 and the N-channel MOS transistor 28 respectively, and symbol S denotes a node connected with drains of the N-channel MOS transistors 27 and 28 connected to the data output terminal 25.
Further, symbols i1 and i2 denote currents flowing through the N-channel MOS transistors 27 and 28 respectively when discharging the data output terminal 25 and the load connected thereto.
The output buffer circuit 1200 according to the second prior art includes the two discharge transistors 27 and 28 entering conducting states with time difference, thereby reducing the peak value of the current flowing into the ground and enabling reduction of noise caused on a ground line.
Operations of the output buffer circuit 1200 according to the second prior art are now briefly described.
FIG. 4 is a timing chart illustrating the operations of the output buffer circuit 1200 according to the second prior art.
First, it is assumed that the potential V.sub.P of the node P is at a low level and the potential V.sub.Q of the node Q is also at a low level at a time t0. Therefore, the potential V.sub.R of the node R is also at a low level. In other words, both N-channel MOS transistors 27 and 28 are in non-conducting states and the P-channel MOS transistor 23 is in a conducting state at the time t0. Therefore, the potential V.sub.S of the node S is at a high level and the data output terminal 25 outputs a high-level signal.
At a time t1, both potentials V.sub.P and V.sub.Q go high in response to read data from a memory cell outputted from a sense amplifier 30. The P-channel MOS transistor 23 enters a non-conducting state and the N-channel MOS transistor 27 enters a conducting state in response to this change. Therefore, the discharge current i1 from the data output terminal 25 and the load connected thereto starts to flow to the N-channel MOS transistor 27. However, the N-channel MOS transistor 28 still remains in the non-conducting state at this point of time.
At a time t2 delayed by the delay time of the delay circuit 26 from the time t1, the potential V.sub.R goes high. In response to this, the N-channel MOS transistor 28 also enters a conducting state and the discharge current i2 starts to flow to the N-channel MOS transistor 28.
Therefore, the currents i1 and i2 flow in temporal dispersion, and hence the peak value of the total discharge current i1+i2 and steepness of a time change thereof are suppressed as compared with the case of feeding a discharge current only through the N-channel MOS transistor 27.
Referring to FIG. 4, dotted lines show the time change of the potential V.sub.S and that of the total discharge current i1+i2 in the case of discharging the data output terminal 25 and the load connected thereto only with the N-channel MOS transistor 27.
Thus, the output buffer circuit 1200 according to the second prior art can reduce the peak value of a discharge current flowing through each data output terminal or relax inclination of a time change thereof, for reducing noise caused on the ground line itself, coupling noise caused between the ground line and the power supply line, and the like.
When the number of simultaneously operating output buffer increases as described above, however, the delay circuit 26 must have a larger delay time for sufficiently reducing the aforementioned noise through the structure of the output buffer circuit 1200 according to the second prior art. In this case, however, the time required for outputting data, i.e., the access time of the semiconductor memory device is deteriorated.
In other words, reduction of the noise is restricted in the structure of the output buffer circuit 1200 according to the second prior art, due to a tradeoff between reduction of the noise and that of the access time.